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AOP-12D multi-function analogue output card user manual

AOP-12D user manual document part n 0127-0146 document reference AOP-12D\..\ 0127-0146.doc document issue level 2.0 manual covers pcbs identified kfa12o rev. b all rights reserved. no part of this publication may be reproduced, stored in any retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or otherwise, without the prior permission, in writing, from the publisher. for permission in the uk contact blue chip technology. information offered in this manual is correct at the time of printing. blue chip technology accepts no responsibility for any inaccuracies. this information is subject to change without notice. all trademarks and registered names acknowledged. blue chip technology ltd. chowley oak, tattenhall, chester, cheshire, ch35 9ex. telephone : (01829) 772000 facsimile : (01829) 772001.
amendment history issue level issue date author amendment details 1.0 9/8/95 sh first approved issue, new front sheet. 2.0 20/12/95 egw addition of emc information to technical section. errors corrected. references to current outputs removed. added layout diagram. earlier part no. was 127-038. filename was ...\ userg.doc
contents blue chip technology ltd. 01270146.doc outline description 1 specification 2 analogue outputs 2 digital input/outputs 3 timers 4 board connectors 4 electromagnetic compatibility (emc) 5 quick installation 7 base address 7 interrupts 7 dma settings 8 fitting the card 8 using the card 9 external input/output connections 9 analogue connections 9 analogue voltage outputs 10 digital connections 11 operation of the card 12 programmable digital input/outputs 12 control codes 13 timers 14 timer initialisation 16 dac section 17 auto channel scanning 18 maps and registers 19 card address map 19 dac control register 19 channel enable registers 20 sample program descriptions 22 qbasic and c examples 22
contents detailed card installation 23 base address 23 interrupts 25 dma settings 26 card layout diagram 27 appendix a - numbering systems 28 binary and hexadecimal numbers 28 base address selection 31 appendix b - pc maps 32 pc xt/at i/o address map 32 pc xt interrupt map 33 pc at interrupt map 34 dma channels 34 appendix c - using dma 35 the dma controller 35 the dma controller registers 37 addressing 40 dma limitations 41 programming example 42
outline description page 1 blue chip technology ltd. 01270146.doc page 1 outline description the AOP-12D is a pc-compatible short card which provides digital inputs and outputs, and analogue outputs. there are 24 ttl compatible programmable digital input/outputs available externally. there are also three programmable timers. one of the timer outputs is available externally to the user. there are 12 analogue outputs available as 10 volts. output resolution is 12 bits. dma data transfer is available on the analogue output channels.
page 2 specification page 2 01270146.doc blue chip technology ltd. specification analogue outputs analogue outputs 12 channels resolution 12 bit monotonic voltage outputs 10 volts @ 10ma maximum one o/p, or 5ma each from all o/ps output error volts 0.5% of span output settling time 3s to 1 lsb data transfer i/o port or dma dma channels supported 1,2 and 3 fastest dma transfer rate 12s per transfer channel selection any or all channels may be selected to be updated dma transfer initialisation software start signal maximum time skew channel 1 to channel 12 144s between channels 12s dma timing source on -board programmable timer
specification page 3 blue chip technology ltd. 01270146.doc page 3 digital input/outputs number of channels 24 digital inputs high level input 2.2 volts minimum current 10a sink low level input 0.8 vol ts maximum current 10a source digital outputs logic high voltage 3.5 volt minimum current 400a source logic low voltage 0.4 volt current 2.5ma sink
page 4 specification page 4 01270146.doc blue chip technology ltd. timers number of timer channels 3 timer usage timer 0 pre-scalar for timer 1 timer 1 timer for dma transfer timer 2 uncommitted (output available) timer 0 resolution 1 m s minimum time 2 m s maximum time 130ms timer 1 resolution timer 0 output value minimum time 4 m s maximum time 2.3 hours timer 2 resolution 1 m s minimum time 2 m s maximum time 130ms board connectors pc isa 8-bit card analogue signals 50 way male `d' type digital signals 50 way idc male box header
specification page 5 blue chip technology ltd. 01270146.doc page 5 electromagnetic compatibility (emc) this product meets the requirements of the european emc directive (89/336/eec) and is eligible to bear the ce mark. it has been assessed operating in a blue chip technology icon industrial pc. however, because the board can be installed in a variety of computers, certain conditions have to be applied to ensure that the compatibility is maintained. it meets the requirements for an industrial environment ( class a product) subject to those conditions. the board must be installed in a computer system which provides screening suitable for the industrial environment. any recommendations made by the computer system manufacturer/supplier must be complied with regarding earthing and the installation of boards. the board must be installed with the backplate securely screwed to the chassis of the computer to ensure good metal-to-metal (i.e. earth) contact. most emc problems are caused by the external cabling to boards. with analogue boards particular attention must be paid to this aspect. it is imperative that any external cabling to the board is totally screened, and that the screen of the cable connects to the metal end bracket of the board and hence to earth. it is recommended that round screened cables with a braided wire screen are used in preference to those with a foil screen and drain wire. use metal connector shells which connect around the full circumference of the screen; they are far superior to those which earth the screen by a simple ?pig-tail?. standard ribbon cable will not be adequate unless it is contained wholly within the cabinetry housing the industrial pc.
page 6 specification page 6 01270146.doc blue chip technology ltd. if difficulty with interference is experienced the cable should also be fitted with a ferrite clamp as close possible to the connector. the preferred type is the chomerics clip -on style, type h8fe-1004-as. it is recommended that cables are kept as short as possible, particularly when dealing with low level signals. ensure that the screen of the external cable is bonded to a good rf earth at the remote end of the cable. failure to observe these recommendations may invalidate the emc compliance. warning this is a class a product. in a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures. emc specification a blue chip technology icon industrial pc fitted with this card meets the following specification: emissions en 55022:1995 radiated class a conducted class a & b immunity en 50082-1:1992 incorporating: electrostatic discharge iec 801-2:1984 performance criteria b radio frequency susceptibility iec 801-3:1984 performance criteria a fast burst transients iec 801-4:1988 performance criteria b
quick installation page 7 blue chip technology ltd. 01270146.doc page 7 quick installation before installing the card into your computer system, there are a number of links which must be set. the settings of these links will depend upon the computer system into which the card is being fitted. users unfamiliar with the settings of links should refer to the section ?detailed card installation?. for those unfamiliar with binary and hexadecimal numbers, a brief explanation is included in the appendices. base address select an unused i/o address range for the card. the card requires a block of 16 contiguous addresses. the base address is set on jumper block jp3. fitting a link is equivalent to a logic ?0?. leaving the link open is equivalent to a logic ?1?. the card is shipped with the default address setting of 300 hex. this is suitable for most small installations. interrupts the dac generates interrupts at the end of a dma transfer. interrupts irq2 to irq7 are provided. the pio and the timer cannot generate interrupts. the interrupt setting is selected by a link on jumper block jp1. if interrupt operation is not required leave the link off.
page 8 quick installation page 8 01270146.doc blue chip technology ltd. dma settings the card can transfer data from memory to the analogue outputs using dma. the settings are controlled by links on jumper blocks jp2 and jp4. dma channels 1 and 3 are provided. jp4 controls the setting of the dma request channels for the dac. jp2 controls the setting of the dma acknowledge channels. the settings must be the same on both jp2 and jp4. if dma operation is not required, the links may left open to allow the unused channels to be used by other cards. the appendix contains a section explaining the use of dma fitting the card once all the links have been set, the card can be installed into the host computer. observe all safety precautions and anti-static precautions. if possible try and locate the card away from 'noisy' cards such as hard disc controllers, network cards and processor cards.
using the card page 9 blue chip technology ltd. 01270146.doc page 9 using the card external input/output connections the AOP-12D has two connectors for external circuitry. the analogue output signals are available at a standard 50 pin d -type connector which protrudes through the end bracket of the printed circuit board. the digital input output signals are presented on a 50 way idc header at the inner end of the printed circuit board. these signals may be brought to a connector on a second bracket the rear cover of the pc using a 50 way ribbon extension cable. filtered connectors are recommended for emc. analogue connections the following table shows the pin out of the d -type analogue connector con1. the pins are arranged in three rows. pin usage pin usage pin usage 1 v output 1 18 no connect 34 v output 12 2 no connect 19 v output 7 35 no connect 3 no connect 20 no connect 36 no connect 4 v output 2 21 no connect 37 no connect 5 no connect 22 v output 8 38 no connect 6 no connect 23 no connect 39 no connect 7 v output 3 24 no connect 40 no connect 8 no connect 25 v output 9 41 no connect 9 no connect 26 no connect 42 no connect 10 v output 4 27 no connect 43 no connect 11 no connect 28 v output 10 44 no connect 12 no connect 29 no connect 45 no connect 13 v output 5 30 no connect 46 no connect 14 no connect 31 v output 11 47 no connect 15 no connect 32 no connect 48 no connect 16 v output 6 33 no connect 49 analogue ground 17 no connect 50 no connect
page 10 using the card page 10 01270146.doc blue chip technology ltd. analogue voltage outputs the analogue output signals from the AOP-12D are available as voltages only, with the ability to supply a limited current. each of the 12 output signals (voutput-1 to voutput-12) has a corresponding analogue ground or 0 volt connection. the voltage outputs are referenced to these connections. measuring output voltages with reference to other ground points (particularly the digital ground) will give electrically noisy results. the voltage output has a span from +10 volts to -10 volts with an output drive of 10ma maximum for any single output and 5ma maximum each for all outputs simultaneously. if large capacitive loads are to be connected to the voltage output, it is recommended that a series resistance of approximately 100 ohms is placed in series with the output voltage to avoid oscillations occurring at the output.
using the card page 11 blue chip technology ltd. 01270146.doc page 11 digital connections the following table shows the pin out of the idc digital signal connector con2. the pins are arranged in two rows. pin signal pin signal 1 dio port a, bit 0 2 dio port a, bit 1 3 dio port a, bit 2 4 dio port a, bit 3 5 dio port a, bit 4 6 dio port a, bit 5 7 dio port a, bit 6 8 dio port a, bit 7 9 dio port b, bit 0 10 dio port b, bit 1 11 dio port b, bit 2 12 dio port b, bit 3 13 dio port b, bit 4 14 dio port b, bit 5 15 dio port b, bit 6 16 dio port b, bit 7 17 dio port c, bit 0 18 dio port c, bit 1 19 dio port c, bit 2 20 dio port c, bit 3 21 dio port c, bit 4 22 dio port c, bit 5 23 dio port c, bit 6 24 dio port c, bit 7 25 digital ground 26 digital ground 27 digital ground 28 digital ground 29 digital ground 30 digital ground 31 timer2 output 32 timer 0 output 33 digital ground 34 digital ground 35 digital ground 36 digital ground 37 digital ground 38 digital ground 39 digital ground 40 digital ground 41 digital ground 42 digital ground 43 digital ground 44 digital ground 45 digital ground 46 digital ground 47 digital ground 48 digital ground 49 digital ground 50 digital ground dio - digital input/output.
page 12 operation of the card page 12 01270146.doc blue chip technology ltd. operation of the card programmable digital input/outputs the AOP-12D includes an nec pd71055 device which is equivalent to an intel 8255 pio. this device provides 24 programmable digital i/o channels. it is suitable for sensing the presence of, or driving ttl connections only. these connections should be kept as short as possible, less than 2 metres is recommended. the digital i/o appears to the pc as four ports. the first three can be set as input or output by writing suitable codes to the fourth control port. these four ports are mapped into the AOP-12D address map as follows: base + 4 programmable digital i/o port a (read/write); + 5 programmable digital i/o port b (read/write); + 6 programmable digital i/o port c (read/write ); + 7 control port (write only). a summary of the codes required to change the operation of the ports are given later. a typical sequence of events to use this feature would be : decide on the input/output mix and write the appropriate code to base + 7. read from the selected output port or write to the selected output port.
operation of the card page 13 blue chip technology ltd. 01270146.doc page 13 control codes the pd71055 can operate in one of 3 modes. the first (mode 0) provides for simple inputs and outputs for three, 8 bit ports. data is written to or read from a specified port (a, b, or c) without the use of handshaking. the following table gives a summary of the most commonly used ?control words? which must be written to the control port to configure the pd71055 i/o ports in mode 0. control word (hex) control word (decimal) set all of port a as set all of port b as set high 4 bits of c as set low 4 bits of c as 80 128 output output output output 81 129 output output output input 82 130 output input output output 83 131 output input output input 88 136 output output input output 89 137 output output input input 8a 138 output input input output 8b 139 output input input input 90 144 input output output output 91 145 input output output input 92 146 input input output output 93 147 input input output input 98 152 input output input output 99 153 input output input input 9a 154 input input input output 9b 155 input input input input mode 1 enables the transfer of data to or from a specified 8 bit port (a or b) in conjunction with strobes or handshaking signals on port c. in mode 2, data is transferred via one bi-directional 8 bit port (a) with handshaking (port c). refer to the pd71055 or i8255 data sheet for full details of the settings and use of modes 1 and 2.
page 14 operation of the card page 14 01270146.doc blue chip technology ltd. timers the AOP-12D includes an nec pd71054 timer chip which is equivalent to an intel 8254. the timer chip contains three independent 16 bit counters which may be operated in different modes. there are five basic modes of operation with each mode providing a different output signal from the three output pins of the device. important timers 0 and 1 are crucial to the operation of the board. the dac section is controlled by the output of these timers so for all operating modes of the dac, these timers must be configured to run. see the section on timer initialisation for code examples to configure these timers. the reference clock for timers 0 and 2 is 1mhz. timer 1 is in series with the output of timer 0. timer 0 is committed as the first divider for dma in the AOP-12D and its output is also available on the external connector. timer 2 is uncommitted in the AOP-12D and its output is available on the external connector. in dma mode, timers 0 and 1 set the rate at which data is dma?d. to set a particular dma rate, use the following equation: note that the 1 mhz clock is divided by 8 by the circuitry giving a reference of 125 khz dma rate (in hz) = 1250000 / divider where ?divider? = (65536 * timer 1 value) + (timer 0 value)
operation of the card page 15 blue chip technology ltd. 01270146.doc page 15 block diagram of timer connections the timer circuit appears to the pc as four ports. these four ports are mapped into the AOP-12D address map as follows: base + 8 timer/counter 0 (read/write). + 9 timer/counter 1 (read/write). + 10 timer/counter 2 (read/write). + 11 control register, (write only). bits 6 and 7 in the control register enable and disable timer 0 and 1, and timer 2. timer 2 1 mhz clock timer 0 timer 2 output connection timer 0 output connection dma transfer control circuit timer 1
page 16 operation of the card page 16 01270146.doc blue chip technology ltd. timer initialisation before the dac section can be operated in any mode timers 0 and 1 must be configured. to do this, follow this sequence of writing to the timer registers output hex 0 to control register (base + 0). this disables timers 0 and 1. read base + 0. this resets the internal state machine logic. output hex 34 to the timer control register (base + 11). this sets timer 0 into mode 2. output 3 to timer 0 count register (base + 8). this writes 3 into the low 8 bits of the 16 bit counter register. output 0 to timer 0 count register (base + 8). this writes 0 into the high 8 bits of the 16 bit counter register. output hex 78 to the timer control register (base + 11). this sets timer 1 into mode 4. output hex 1 to timer 1 count register (base + 9). this writes 1 into the low 8 bits of the 16 bit counter register. output hex 0 to time 1 count register (base + 9). output hex 40 to control register 1 (base + 0). in basic the initialisation sequence would look like this: 10 out ( baseadd + 0,&h0) 20 dummy% = inp( baseadd) 30 out ( baseadd + 11,&h34) 40 out ( baseaad + 8,&h03) 50 out ( baseaad + 8,&h00) 60 out ( baseadd + 11,&h78) 70 out ( baseadd + 9,&h03) 80 out ( baseadd + 9,&h00) 90 out(baseadd,&h40)
operation of the card page 17 blue chip technology ltd. 01270146.doc page 17 dac section the digital to analogue converter is accessed as 4 ports. these ports are mapped into the pc at the following addresses. base + 0 dac control register + 1 channel enable register 1 + 2 channel enable register 3 + 3 dac output register the dac is 12 bits wide, therefore two write operations are required to the dac output register to load the required value. the low 8 bits are sent first followed by the high 4 bits. output value output voltage 0 -10 v 2048 0 v 4095 +10 v the dac section operates in one of two basic modes, i/o or dma. to send data to the dac in i/o mode use the following sequence: initialise the timer (see timer initialisation above). write 0 to base + 1 and base + 2, this enables all the channels. read base + 0 , this resets the internal state machine. write the low 8 bits of the dac data into base + 3. write the high 4 bits of the dac data into base + 3. write the channel number to update (1 to 12) to base + 0. write 0 to base + 0.
page 18 operation of the card page 18 01270146.doc blue chip technology ltd. to operate in dma mode updating a single channel use the following sequence: initialise the timer, as above. program timers 0 and 1 for the required output rate. write 0 to base + 1 and base + 2, this enables all the channels. program the dma controller. write the channel number (1 to 12) + 240 to base + 0. start the dma operation by reading base + 0. auto channel scanning in dma mode it is possible to output to all 12 channels by setting the auto channel scanning bit in channel enable register 2. when this bit is set, after each dma transfer the channel number will be incremented so the next dma transfer will take place on the next channel. when the channel reaches 12, it will continue to increment as if channels 13-16 were present, before resetting to channel 1. to use this mode, the software must set-up a multi-dimensional array to store the data for 16 channels (12 real + 4 phantom channels). in basic: dim dataarray%(numsamples,16) in c: int dataarray[ numsamples][16] software example 4 demonstrates the use of channel scanning.
maps and registers page 19 blue chip technology ltd. 01270146.doc page 19 maps and registers card address map base + n r/w section function 0 w dac dac control register 0 r dac initiate dma transfer / reset state machine logic 1 w dac channel enable register 1 2 w dac channel enable register 2 3 w dac dac output data 4 r/w pio pio port a data 5 r/w pio pio port b data 6 r/w pio pio port c data 7 r/w pio pio control register 8 r/w timer timer 0 count register 9 r/w timer timer 1 count register 10 r/w timer timer 2 count register 11 r/w timer timer control register dac control register (base + 0) data bit function 0 dac channel select / update bit 0 *1 1 dac channel select / update bit 1 *1 2 dac channel select / update bit 2 *1 3 dac channel select / update bit 3 *1 4 0 = disable dma request 1 = enable dma request 5 0 = i/o mode 1 = dma mode 6 0 = disable dac control timers (timers 0 and 1) 1 = enable dac control timers (timers 0 and 1) 7 0 = disable uncommitted timer 2 1 = enable uncommitted timer 2 *1 writing 0 into all four bits updates the previously selected dac output
page 20 maps and registers page 20 01270146.doc blue chip technology ltd. channel enable registers register 1 (base + 1) data bit function 0 0 = enable channel 1 output 1 = disable channel 1 output 1 0 = enable channel 2 output 1 = disable channel 2 output 2 0 = enable channel 3 output 1 = disable channel 3 output 3 0 = enable channel 4 output 1 = disable channel 4 output 4 0 = enable channel 5 output 1 = disable channel 5 output 5 0 = enable channel 6 output 1 = disable channel 6 output 6 0 = enable channel 7 output 1 = disable channel 7 output 7 0 = enable channel 8 output 1 = disable channel 8 output
maps and registers page 21 blue chip technology ltd. 01270146.doc page 21 register 2 (base + 2) data bit function 0 0 = enable channel 9 output 1 = disable channel 9 output 1 0 = enable channel 10 output 1 = disable channel 10 output 2 0 = enable channel 11 output 1 = disable channel 11 output 3 0 = enable channel 12 output 1 = disable channel 12 output 4 0 = disable automatic channel scanning *1 1 = enable automatic channel scanning 5 0 = enable dma cycle mode *2 1 = disable dma cycle mode 6 not used, always write 0 7 not used, always write 0 *1 when this bit is 1 the selected dac channel will increment after each dac update ( dma mode only) *2 when this bit is 1 the auto-initialise function of the dma control is disabled (see using dma for a description of auto-initialise)
page 22 sample program descriptions page 22 01270146.doc blue chip technology ltd. sample program descriptions the disk supplied with the card contains several example programs to demonstrate the various operating modes. qbasic and c examples example1.bas example1.c these demonstrate the simple i/o mode to output a single value to one analogue output channel. example2.bas example2.c these demonstrate reading and writing to the digital i/o. example3.bas example3.c these demonstrate the dma mode to output a sine wave to a single analogue output channel example4.bas example4.c these demonstrate the dma mode to output a sine wave to all twelve analogue output channels.
detailed card installation page 23 blue chip technology ltd. 01270146.doc page 23 detailed card installation before installing the card into your computer system, there are a number of links which must be set. the settings of these links will depend upon the computer system into which the card is being fitted. the positions of these links are shown on the card layout diagram towards the end of this manual base address the card may be located in any 62 pin slot in the pc motherboard but must be set up to appear at a specified address in the i/o port map. available positions are shown in the ibm-pc technical reference guide. however, for those who do not possess a copy of this document, a good place is the location normally allocated to the prototyping card as supplied by ibm. this address is 300 hex which is the factory default setting. however, no two devices should be used while set to the same address since contention will occur and neither card will work. if your machine contains a card with a conflicting address then another reasonably safe address to use is 200 to 21f hex . a set of links are provided on the card to set the base address within the ibm- pc i/o port map. the address is in binary with the presence of a link representing a 0 and the absence of a link representing a 1.
page 24 detailed card installation page 24 01270146.doc blue chip technology ltd. to set the base address to 300 hex , locate the jumper block jp3 labelled base address. set the following pattern on the links as indicated below with connector con2 on right hand side and the gold fingers to the lower edge.:- other examples are: address hex 200 address hex 240
detailed card installation page 25 blue chip technology ltd. 01270146.doc page 25 interrupts the dac generates an interrupt signal at the end of a dma transfer. the interrupt is selected on jumper block jp1. the diagram below shows the dac set to produce an interrupt request on irq3. the second example shows the setting if the dac generates interrupt request irq6.
page 26 detailed card installation page 26 01270146.doc blue chip technology ltd. dma settings the dma selection is set on two sets of jumper blocks, jp2 and jp4. jp4 controls which channel the dac uses to request direct memory access. only channels 1,2 and 3 are available. jumper jp2 sets the channel on which the dma controller acknowledges the request. it is essential that the pattern of links on the two jumper blocks correspond. the example below shows the link settings for the dac to generate drq1 and receive dack1. 1 2 3 1 2 3
detailed card installation page 27 blue chip technology ltd. 01270146.doc page 27 card layout diagram kfa12o card layout showing selector link positions
page 28 appendix a page 28 01270146.doc blue chip technology ltd. appendix a - numbering systems binary and hexadecimal numbers the normal numbering system is termed decimal because there are ten possible digits (0 to 9) in any single column of numbers. decimal numbers are also referred to as numbers having a base 10. when counting, the numbers increment in the units column from 0 up to 9. the next increment resets the units column to 0 and carries over 1 into the next column. this 1 indicates that there has been a full ten (the base number) counts in the units column. the second column is therefore termed the ?tens? column. it is more convenient when programming to use a number system that provides a clearer picture of the hardware at an operational or register level. the two most common number systems used are binary and hexadecimal. these two systems provide an alternative representation to decimal numbers. for a binary number there are only 2 possible values (0 or 1) and as a result binary numbering is often known as base 2. when counting in binary numbers, the number increments the units column from 0 to 1. at the next increment the units column is reset to 0 and 1 is carried over to the next column. this column indicates that a full two counts have occurred in the units column. now the second column is termed the ?twos? column. hexadecimal numbers may have 16 values (0 to 9 followed by the letters a to f). it is also known as a system with the base 16. with this counting system the units increment from 0 to 9 as with the decimal system, but at the next count the units column increments from 9 to a and then b, c and so on up to f. after f the units column resets to 0 and the next column increments from 0 to 1. this 1 indicates that sixteen counts have occurred in the units column. the second column is termed the ?sixteen?s? column.
appendix a page 29 blue chip technology ltd. 01270146.doc page 29 the following table shows how the three systems indicate successive numbers decimal binary hexadecimal base 10 base 2 base 16 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 2 0 0 0 1 0 0 2 0 3 0 0 0 1 1 0 3 0 4 0 0 1 0 0 0 4 0 5 0 0 1 0 1 0 5 0 6 0 0 1 1 0 0 6 0 7 0 0 1 1 1 0 7 0 8 0 1 0 0 0 0 8 0 9 0 1 0 0 1 0 9 1 0 0 1 0 1 0 0 a 1 1 0 1 0 1 1 0 b 1 2 0 1 1 0 0 0 c 1 3 0 1 1 0 1 0 d 1 4 0 1 1 1 0 0 e 1 5 0 1 1 1 1 0 f 1 6 1 0 0 0 0 1 0 1 7 1 0 0 0 1 1 1 1 8 1 0 0 1 0 1 2 1 9 1 0 0 1 1 1 3 2 0 1 0 1 0 0 1 4 notice how the next higher column does not increment until the lesser one to its right has overflowed. binary representation is ideally suited where a visual representation of a computer register or data is needed. each column is termed a bit (from b inary dig it ). only five bits are shown in the above table. with larger numbers, more bits are required. normally bits are arranged in groups of eight termed bytes. by definition there are 8 bits per byte. each bit (or column) has a value. in the binary table above the rightmost or least significant column each digit has a value of 1. each digit in the next column has a value of 2, the next 4, then 8 and so on.
page 30 appendix a page 30 01270146.doc blue chip technology ltd. the following diagram illustrates this. bit no 7 6 5 4 3 2 1 0 decimal value 128 64 32 16 8 4 2 1 to determine the decimal value of a binary pattern, add up the decimal number of each column containing a binary ?1?. bit no 7 6 5 4 3 2 1 0 decimal value 128 64 32 16 8 4 2 1 binary number 1 1 0 0 0 1 1 0 the above example shows the binary pattern that is equivalent to 198 decimal . the binary string defining a byte can be unwieldy. to make it less error prone, the 8 bits forming a byte are divided into two groups of 4 bits, known as nibbles. with four bits there are 16 possible numeric combinations (including zero). a convenient method of representing each nibble is to use the hexadecimal base 16 system. when converting binary to hex, the byte is divided into nibbles each represented by a single hex digit. this technique is applied to the selection of the base address for the circuit board. the following diagram illustrates the construction of a hex number. bit no 7 6 5 4 3 2 1 0 nibble value 8 4 2 1 8 4 2 1 binary number 1 1 0 0 0 1 1 0 ???-?a??????? ?????a?????? hexadecimal: c 6 hexadecimal upper nibble = (1 x 8) + (1 x 4) + (0 x 2) + (0 x 1) = 12 lower nibble = (0 x 8) + (1 x 4) + (1 x 2) + (0 x 1) = 6 the resulting value is c6 hex , since 12 decimal is c hex .
appendix a page 31 blue chip technology ltd. 01270146.doc page 31 base address selection each column can be physically represented on the board by a pair of pins. in practice, the boards cover a range of addresses (usually 16 decimal ). therefore the low order four bits are not included, but two higher order bits are added. this gives an address range of 0 to 3f0 hex . the following diagram shows a typical set of pins. here a link is fitted to denote a binary or logic ?0?, or left open to indicate a binary or logic ?1?. the example shows a base address setting of 300 hex .
page 32 appendix b page 32 01270146.doc blue chip technology ltd. appendix b - pc maps pc xt/at i/o address map address allocated to: 000-01f dma controller 1 (8237a-5) 020-03f interrupt controller 1 (8259a) 040-05f timer (8254) 060-06f keyboard controller (8742) control port b 070-07f rtc and cmos ram, nmi mask (write) 080-09f dma page register (memory mapper) 0a0-0bf interrupt controller 2 (8259) 0f0 clear npx (80287) busy 0f1 reset npx (80287) 0f8-0ff numeric processor extension (80287) 1f0-1f8 hard disk drive controller 200-207 reserved 278-27f reserved for parallel printer port 2 2f8-2ff reserved for serial port 2 300-31f reserved 360-36f reserved 378-37f parallel printer port 1 380-38f reserved for sdlc communications, bisync 2 3a0-3af reserved for bisync 1 3b0-3bf reserved 3c0-3cf reserved 3d0-3df display controller 3f0-3f7 diskette drive controller 3f8-3ff serial port 1
appendix b page 33 blue chip technology ltd. 01270146.doc page 33 pc xt interrupt map number allocated to: nmi parity 0 timer 1 keyboard 2 reserved 3 asynchronous communications (secondary) sdlc communications 4 asynchronous communications (primary) sdlc communications 5 fixed disk 6 diskette 7 parallel printer
page 34 appendix b page 34 01270146.doc blue chip technology ltd. pc at interrupt map level allocated to: cpu nmi parity or i/o channel check ctlr 1 ctlr 2 (interrupt controllers) irq 0 timer output 0 irq 1 keyboard (output buffer full) irq 2 interrupt from ctlr 2 irq 8 real-time clock interrupt irq 9 s/w redirected to int 0ah ( irq 2) irq 10 reserved irq 11 reserved irq 12 reserved irq 13 co.-processor irq 14 fixed disk controller irq 15 reserved irq 3 serial port 2 irq 4 serial port 1 irq 5 parallel port 2 irq 6 diskette controller irq 7 parallel port 1 dma channels 0 memory refresh 1 spare 2 floppy disk drive 3 spare
appendix c page 35 blue chip technology ltd. 01270146.doc page 35 appendix c - using dma direct memory access or dma is a process by which data can be transferred directly from the memory of the pc into an i/o card or directly from the i/o card into the pc memory with no intervention from the processor. this can greatly increase the throughput of data and at the same time, reduce the overhead of processor time. the dma controller dma is controlled by the pc using one of two dma controllers. the dma controllers are intel 8237 or compatible devices, each containing four channels. the first one is used for byte transfers in the bottom 1 mb of system memory, the second can transfer words into the bottom 16 mb. blue chip technology boards only allow dma channels 1 or 3 on the first controller to be used. normally channel 0 is reserved for memory refresh control and channel 2 is used by the floppy disk drives. in order to begin a dma transfer, first the i/o board must be configured to enable dma operation - consult the relevant section of the manual on how to do this. secondly, the dma controller must be programmed to begin the transfer. the dma controller is programmed by writing to i/o ports in much the same way as the card is programmed.
page 36 appendix c page 36 01270146.doc blue chip technology ltd. these port locations are fixed for all pcs as follows:- i/o address read/ write description 0000h r/w dma channel 0 current address 0001h r/w dma channel 0 current word count 0002h r/w dma channel 1 current address 0003h r/w dma channel 1 current word count 0004h r/w dma channel 2 current address 0005h r/w dma channel 2 current word count 0006h r/w dma channel 3 current address 0007h r/w dma channel 3 current word count 0008h r/w command/status register 0009h r/w dma request register 000ah r/w dma single bit mask register 000bh r/w dma mode register 000ch r/w dma clear byte pointer 000dh r/w dma master clear 000eh r/w clear mask register 000fh r/w dma write all mask register bit 0081h r/w page register dma channel 2 0082h r/w page register dma channel 3 0083h r/w page register dma channel 1
appendix c page 37 blue chip technology ltd. 01270146.doc page 37 the dma controller registers in order to begin a dma transfer there are several registers within the dma controller which need to be configured. the relevant registers are described below:- mode register port 0bh 7 mode bit 1 6 mode bit 0 5 auto inc/ dec 4 auto init. 3 trans mode bit 1 2 trans mode bit 0 1 chan sel bit 1 0 chan sel bit 0 mode bits bit1 bit 0 function 0 0 demand mode 0 1 single mode 1 0 block mode 1 1 not used the mode bits set the particular mode for the channel, normally this will be set for single mode. auto inc/dec 0 increment address 1 decrement address when a dma transfer takes place, the transfer address can either be incremented or decremented after each transfer selected by this bit.
page 38 appendix c page 38 01270146.doc blue chip technology ltd. auto initialise 0 disabled 1 enabled if set to auto initialise, when the dma transfer reaches the end of a block, the dma controller will reload all its initial values and repeat the transfer. this is useful on analogue out boards for outputting continuous wave forms. transfer mode bit 1 bit 0 function 0 0 verify transfer 0 1 write transfer 1 0 read transfer 1 1 not used use write transfer if the i/o board is generating a value to be written into memory (analogue in), use read transfer when values are written from memory into the board (analogue out). channel select bit 1 bit0 function 0 0 dma channel 0 select 0 1 dma channel 1 select 1 0 dma channel 2 select 1 1 dma channel 3 select
appendix c page 39 blue chip technology ltd. 01270146.doc page 39 mask register port 0ah 7 not used 6 not used 5 not used 4 not used 3 not used 2 clr/set mask 1 mask bit 1 0 mask bit 0 clr/set mask 0 clear mask bit 1 set mask bit mask bit 1 bit 0 function 0 0 channel 0 select 0 1 channel 1 select 1 0 channel 2 select 1 1 channel 3 select setting a mask bit for a particular channel disables the dma operation on that channel. status register port 0bh read 7 chan 3 dma rq 6 chan 2 dma rq 5 chan 1 dma rq 4 chan 0 dma rq 3 chan 3 at tc 2 chan 2 at tc 1 chan 1 at tc 0 chan 0 at tc dma rq 1 = dma request made on channel n at tc 1 = channel n has reached terminal count ( tc) the status register indicates which channels have made a dma request and which channels have reached terminal count. terminal count is set when the number of bytes specified by the transfer length register have been transferred.
page 40 appendix c page 40 01270146.doc blue chip technology ltd. clear byte pointer flip flop port 0ch any write to this port resets the byte pointer flip flop. this ensures that the first write to the start address or transfer length registers will go into the lsb of that register. dma transfer start address ports 00h, 02h, 04h, 06h sets the 16 bit start address for the dma transfer, send ls byte first. transfer length ports 01h, 03h, 05h, 07h sets the 16 bit length of the dma transfer, send ls byte first. page register ports 83h, 81h, 82h sets the upper eight bits of the physical memory address of the dma transfer. addressing in order for dma to operate correctly the page register and start address register should be set-up to inform the dma controller where in memory the transfer is to take place. the intel x86 family of microprocessors address memory using 2 address pointers called segment and offset, this is called a logical address. the microprocessor combines the segment and offset to produce a physical address which it uses to access the memory. if we consider a pc which has 1mbyte of memory, each memory location will have a physical address of 0 to 1048575 (or 0 to fffff hex ). it has a logical range of 0000:0000 to f000:ffff. the colon is commonly used to separate the segment address from the offset address ( segment:offset)
appendix c page 41 blue chip technology ltd. 01270146.doc page 41 to convert from a logical address to a physical address use the following formula: physical address = (segment * 16) + offset most programming languages allow access to the segment and offset addresses of variables in memory. for example, in quick basic the following commands can be used: dim dat%(1000) seg = varseg( dat%) offs = varptr( dat%) in this example, the variables ? seg? and ? offs? would contain the segment and offset addresses of the array ? dat%?. in order to pass this address to the dma controller the segment and offset values need to be converted into dmapage and dmaoffset addresses as follows: phyadd = ( seg * 16) + offs dmapage = ( phyadd / 65536) and 15 dmaoffset = phyadd and 65535 dma limitations the dma controller is only capable of incrementing or decrementing the dmaoffset address, the dmapage value is fixed throughout the transfer. this means that a maximum of 64k bytes can be transferred in one operation.
page 42 appendix c page 42 01270146.doc blue chip technology ltd. programming example to set-up a dma transfer the following program sequence is required: define an area of memory for the transfer set-up the i/o board for dma operation disable the dma channel being used. load the start address into page register. this is the start address register for the dma channel being used. load the length count into the transfer length register. note that the dma controller only transfers 8 bits at a time, each value written to an analogue out board or read from an analogue in board is 2 bytes long so the transfer length will be twice the number of samples to be taken. load the mode for the selected dma channel. enable the dma channel. the following extract from a quick basic program demonstrates how to program the dma controller for a write transfer.
appendix c page 43 blue chip technology ltd. 01270146.doc page 43 2000 rem program the dma controller 2005 rem first extract the segment and offset address of our data 2010 seg = varseg( dat%(0)) 2020 offs = varptr( dat%(0)) 2025 rem transfer the logical segment:offset address 2027 rem into a physical page:offset address 2030 page& = seg1% and &hf000 2040 page& = page& / 4096 2050 page& = page& and 15 2060 offset& = seg 2070 offset& = offset& * 16 2080 offset& = offset& + offs 2090 offset& = offset& and 65535 2100 rem setup the dma registers. 2105 out (&ha),7: rem disable dma channel 3 2110 out (&hc), 0: rem reset byte select ff 2120 out (& hb), &h47: rem auto inc on ch3,write transfer, single mode 2130 out (&h82), page&: rem set page for dma ch3 2150 out (&h6), ( offset& and 255): rem set up start for ls 8 bits 2160 out (&h6), ( offset& and &hff00) / 256: rem set up start for ms 8 bits 2170 out (&h7), length% and 255: rem byte count ls 8 bits 2180 out (&h7), length% / 256: rem byte count ms bits 2190 out (&ha), 3: rem enable dma txfer 2200 return

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